The present invention relates to the field of memory-related structures. Specifically, the present invention relates to testing tunnel oxide on a memory-related structure.
Presently, electronic memories come in a variety of forms and serve a variety of purposes. For example, one type of memory is flash memory. Generally, flash memories are used for easy and fast information storage in devices such as digital cameras and home video consoles. It is used more as a hard drive than as random access memory (RAM). In fact, flash memory may be considered a solid state storage device (e.g., no moving parts-everything is electronic).
In general, flash memory is a type of electrically erasable programmable read-only memory (EEPROM). It has a grid of columns and rows with a cell that has two transistors at each intersection. The two transistors are separated from each other by a thin tunnel oxide (TOX) layer. One of the transistors is a floating gate, and the other one is a control gate. The floating gate""s only link to the row is through the control gate. As long as the link is in place, the cell has a value of one. To change the value to a zero requires a process called Fowler-Nordheim (FN) tunneling.
FN tunneling is used to alter the placement of electrons in the floating gate. For example, an electrical charge is applied to the floating gate and drains to the ground. This charge causes the floating-gate transistor to act similar to an electron gun. That is, the electrons are pushed through and trapped on the other side of the TOX layer, giving it a negative charge. These negatively charged electrons act as a barrier between the control gate and the floating gate. A cell sensor then monitors the level of the charge passing through the floating gate. If the flow through the gate is greater than 50 percent of the charge, then it has a value of one. However, when the charge passing through the gate drops below the 50 percent threshold, the value changes to zero. Normally, a blank EEPROM has all of the gates fully open, giving each cell a value of one.
The electrons in the cells of a flash-memory can be returned to normal (e.g., one) by the application of an electric field (e.g., a higher voltage charge). Furthermore, flash memory utilizes in-circuit wiring to apply the electric field either to the entire chip or to predetermined sections known as blocks. This electrical field erases the target area of the chip, which can then be rewritten. Therefore, flash memory works much faster than traditional EEPROMs because instead of erasing one byte at a time, it erases a block or the entire chip. In addition, flash memory will maintain its data without an external source of power. Thus, it is extremely useful with removable memory media such as digital cameras, digital music players, video consoles, computers, and the like.
In order for a flash memory-related structure to operate at peak performance, the memory-related structure manufacturing process needs to be as flawless as possible. Any variations in the memory-related structure, such as TOX deformation, damage to the stack gate edge, damage to the source/drain, damage due to the self-aligned-source (SAS) etch, or the like, may result in the memory-related structure operating at a sub-standard level. That is, as shown in FIG. 1, instead of the memory-related structure having a normal erase profile 110 (as compared with program profile 105 by arrows 130). The threshold voltage (VT) application shows a memory-related structure having a fast erase bit tail 120 (e.g., an uneven erase voltage profile). This fast erase bit tail may result from difficulty in electron control during application of the threshold voltage (e.g., for erasing of the memory) allowing for the memory-related structure to be erased at a much lower threshold voltage thereby possibly causing the memory-related structure to store information incorrectly or not at all.
To ensure that memory-related structures do not have an uneven erase profile 120 (e.g., a fast erase bit tail), the manufactured memory-related structure is tested to ensure that any fast erase bit issues are resolved. In some cases the resolution involves discarding the memory-related structure. In other cases, if a defect such as a segregated edge defect is found in the memory-related structure a post oxidation process (POP) is applied. However, POP may cause TOX encroachment on the channel. Additionally, the amount of time required for POP is not standard. That is, the process varies between memory-related structures.
Due to the post manufacturing testing of fast erase bits in memory-related structures, error detection cannot be accomplished until the entire manufacturing process has been completed. Thus, if a specific step in the process is malfunctioning or is the cause of errors, the manufacturer would not know until both manufacturing time and money has been spent on the damaged memory-related structure. Therefore, the cost of the memory-related structures may be higher than necessary to cover the costs associated with a low yield in a manufacturing cycle. Thus, both the manufacturer and the consumer are forced to spend more due to the inefficiencies of the present manufacturing and testing techniques.
Thus, a need exists for a method and system for testing tunnel oxide on a memory-related structure. A further need exists for a method and system for testing tunnel oxide on a memory-related structure that can be utilized to detect errors throughout the memory-related structure manufacturing process. Yet another need exists for a method and system for testing tunnel oxide on a memory-related structure which can resolve an error in the memory-related structure during the manufacturing process thereby increasing yield. A further need exists for a method which meets the above needs and which is compatible with existing memory manufacturing processes.
The present invention provides, in various embodiments, a method and system for testing tunnel oxide on a memory-related structure. Furthermore, the present invention provides a method and system for testing tunnel oxide on a memory-related structure that can be utilized to detect errors throughout the memory-related structure manufacturing process. Additionally, the present invention provides a method and system for testing tunnel oxide on a memory-related structure which can resolve an error in the memory-related structure during the manufacturing process thereby increasing yield. Moreover, the present invention provides a method which meets the above needs and which is compatible with existing memory manufacturing processes.
Specifically, in one embodiment, the present invention accesses a memory-related structure during a manufacturing process. Next, the present embodiment applies a constant voltage to a gate of the memory-related structure. The present embodiment then measures a first gate current for the memory-related structure when the constant voltage is initially applied, to obtain a first value. Next, the present embodiment measures a second gate current for the memory-related structure a period of time after the constant voltage is initially applied to obtain a second value. A calculation of ratio of the second value to the first value is then performed. The present embodiment then generates a graph of the first value and the ratio of the second value to the first value as a function of time, wherein a decrease in the graph signifies stress induced electron trapping behavior of the tunnel oxide.